## Alok Joshi* , Dewansh Aditya Gupta** and Pravriti Jaipuriyar**## |

Calculations needed | Radix-2 | Direct summation |
---|---|---|

Number of additions | 32 | 256 |

Number of subtractions | 32 | - |

Number of Multiplications | 32 | 256 |

Total number of calculations | 96 | 512 |

It is later implemented using radix-2 algorithms which have better efficiency and time complexity. The comparison has been shown in Table 1.

ADC and DAC is an essential block in OFDM used in receiver and transmitter respectively. DAC is used in OFDM as after the application of IFFT (can apply only on digital data) in transmitter block the signal is transmitted. And the transmission medium is air thus it is required to convert the digital data obtained from the previous block to analog signal. Similarly, the ADC block is used after the FFT block in the receiver.

Many designs were modeled and simulated like Generic ADC and DAC, flash ADC, SAR (successive approximation register ADC), pipelined ADC, etc. Suarez [15] in “Behavioral Modeling of Data Converters using Verilog” had stated that these ADCs are modeled using transistor level modeling which can be useful up to 16-bits but for higher bits the model becomes a lot complex making the design impractical. In generic ADC, there is a mismatch between ADC units which are later removed using dynamic element match (DEM).

Flash ADC is designed using high-speed comparator in a cascade fashion. It can be used up to 8-bit resolution because for higher resolution the design becomes complex and consumes more power, but these are ideal for devices requiring large bandwidth.

An ADC (N bits) requires N comparison periods as it starts the next conversion only after the previous one is complete. Pipelined ADC is most popular ADC architecture with the resolution of fewer bits at faster sample rates and of more bits at the lower rates. Ashraf [16] in 2016 designed an 8-bit SAR ADC with an input voltage of 1.2-V. The SAR control logic was designed asynchronously using Verilog coding. The design was implemented in Cadence Virtuoso using 1.8-nm technology. Designing of low power comparator was achieved which results in overall power consumption of 0.75 mW.

A 10-bit DAC with (6+4) bit segmentation was designed in 2006 by Murali Shanmugasundaram and Shanthi Pavan [17]. The simulations run on full transistor level schematic as well as on the macro design over a range of frequencies. This design uses current controlled current sources which is time-varying in nature and thus reduces the simulation time and increases simulation speed. It was implemented in a 0.35um CMOS process. In 2015, Santhanalakshmi and Yashoda [18] also designed a low power SAR ADC using Verilog-A and proved that bypass window technique is more efficient with a lesser number of transitions, i.e., 3 over 4.

Menzter and Wey [19] developed a mixed signal model of a 10-bit pipelined ADC using Verilog. The overall aim of this project was to identify design flaws based on input/output tests. Implementation of FIR filter was done using onboard ADC-DAC and FPGA.

To optimize design and computations it was also modeled using MATLAB and Simulink [20]. Although transistor level modeling is the most appropriate approach for mixed-signal circuits, but alternate modeling is required to avoid the complexity and long computation time.

The ADC results in a ratiometric value. Analog to digital conversions totally depend on the system voltage. Here the ADC assuming maximum voltage to be 10 V is converted to 1023 and any value less than 10 V will be a ratiometric value correspondingly after quantization.

Fig. 2 illustrates the butterfly structures of radix-2 for 16-point. The basic butterfly structure is implemented in the design of 16-point FFT.

The radix-2 is computed by dividing the Eq. (2) into odd and even terms as mentioned,

But [TeX:] $$W_{M}^{2}=W_{M / 2}$$. Using this substitution, the above equation becomes:

Where

and

and

It implies F_{1} (k) and F_{2} (k) are periodic, with M/2 period.

Hence,

By using Eqs. (14) and (15) we compute radix-2 in our program.

Since the input values are complex therefore two different arrays one for real and the other for the imaginary part have been used.

The twiddle factors which are used in FFT/IFFT blocks are generated using the CORDIC algorithm. Each time while performing the calculation using butterfly structure the angle which is needed is passed to the CORDIC algorithm which gives the sine and cosine of the angle except that in the last stage. In the last stage, the twiddle factor is 1 always, therefore the direct value is saved for cosine and sine, i.e., sine of the angle is 0 and cosine of the angle is 1.

Saving the value 1 in a variable makes it easy to compute the values in the last stage which reduces time by 4 times while using the CORDIC algorithm in the fourth (last) stage of 16-point FFT. Thus, in the last stage, both the complexity as well as time taken is reduced.

The code for radix-2 written in Verilog is universal, i.e., on varying the number of data and data values the design calculates FFT itself, so this can be used for calculating any point-FFT. The output has been shown in Figs. 3–7. The final output comes at 4015 ns. But extra delays were added just for the sake of proper visibility in Fig. 7.

Figs. 3–7 show the FFT simulation of 16-point input using radix-2 algorithm. The parameter a_re, a_im, b_re, and b_im are the outputs of the radix-2 butterfly structure as shown in Fig. 8.

The output result obtained from this proposed work is compared with MATLAB simulations in Fig. 9 using the same algorithm. The MATLAB simulation is used for verification of results (in Fig. 9, ‘x’ is the input variable and ‘y’ is the output variable).

It has been observed that the result of the design simulated using Verilog on ModelSim is almost the same as the results obtained in MATLAB. The comparisons of results of 16-point FFT using Verilog and MATLAB are mentioned in Table 2.

Table 2.

Series no. | Input values | Verilog outputs | MATLAB output | ||
---|---|---|---|---|---|

Real part | Imaginary part | Real part | Imaginary part | ||

0 | 1+0j | 78 | 63 | 78 | 63 |

1 | 2+2j | -10.9914 | 29.8618 | -11.1115 | 29.8472 |

2 | 3+5j | -33.6733 | -23.6722 | -33.6777 | -23.6777 |

3 | 5+7j | 1.59562 | -9.0683 | 1.6521 | -8.9644 |

4 | 7+3j | -18.9993 | -3.99728 | -19 | -4 |

5 | 4+3j | -0.735838 | -35.0674 | -0.656 | -35.1078 |

6 | 0+1j | 22.7445 | -2.12186 | 22.7487 | -2.1213 |

7 | 1+5j | 15.3225 | 13.9488 | 15.1809 | 14.0125 |

8 | 3+4j | -1.99931 | 4.99919 | -2 | 5 |

9 | 2+0j | -6.31809 | 2.55834 | -6.2022 | 2.5792 |

10 | 9+3j | 1.67653 | 11.6751 | 1.6777 | 11.6777 |

11 | 18+8j | -23.3902 | 3.0728 | -23.4511 | 2.9644 |

12 | 6+4j | 10.9993 | -19.9977 | 11 | -20 |

13 | 8+2j | 6.04157 | -17.3395 | 5.9697 | -17.3186 |

14 | 9+14j | -26.741 | 2.12374 | -26.7487 | 2.1213 |

15 | 0+2j | 2.46896 | -19.9476 | 2.618 | -20.0125 |

The input signal is analog which takes in values from +10 V to -10 V and converts them to +1023 to - 1023 which comes as output from the digital signal. Any value greater than 10 V will be limited to its maximum valu, i.e., +1023. Similarly, any value lower than -10 V will be limited to -1023. The signal gets modulated using a carrier signal and the signal is quantized at few intervals. And the reverse procedure is used for implementing DAC. The simulation result is shown in Figs. 10 and 11. The simulation contains conversion of analog to digital values and reconstruction of digital values back to analog again.

In Fig. 10, the transcript shows the input analog signal (‘analog value’), its converted digital signal (‘digital data’) and finally the reconstructed analog signal (‘reconstructed value’) from digital data. Fig. 11 shows the wave simulation (‘c’ is the input analog signal, ‘result_r’ is converted digital signal and ‘result’ is the reconstructed analog signal.).

Nowadays OFDM is an important technology that supports the latest standards of wireless communication. To achieve high data rate, we use OFDM in LTE, WiMAX and WLAN, etc. The main modules of an OFDM system, i.e., the FFT and the IFFT, A/D and D/A have been simulated successfully using radix-2 algorithm and reducing the complex mathematics.

This design works better for large N (in N-point FFT) than radix-M (M>2) because the number of multiplications, addition and subtraction is equal to one in radix-2 while the number of multiplications is more in others thus leading to a more complex design. Also, the last stage of the design is much more time efficient than the existing designs (since the time taken is optimized in the last stage).

For A/D and D/A systems, we implemented the architecture using some common algorithms which include simple mathematics reducing its complexity. The proposed FFT design is both speed and time efficient. It is a method in which the resources have been used in an optimized way.

The high data rate requirement in wireless communication has increased exponentially lately. In this paper, we take a review on the traditional concept in terms of its disadvantages and advantages and have tried to improve them. The future networks will continue to rely on OFDM/OFDMA for satisfying its need.

He has received B.E. degree in Electronics and Communication Engineering from G.B. Pant Enggineering College (Hemvati Nandan Bahuguna Garhwal University), Uttarakhand, India in 2001 and M.Tech. in Digital Communication from Uttar Pradesh Technical University, Lucknow, India in 2006. He received Ph.D. degree from Jaypee University of Information Technology in 2014, in the area of wireless communications. He has total teaching experience of 15 years in various technical universities in India. Currently he is working with Jaypee Institute of Information Technology, Noida, India. His research interests are MIMO OFDM systems.

He received his B.Tech. degree in Electronics and Communication Engineering from Jaypee Institute of Information Technology, Noida, India in 2016. He is currently working as a Software Engineer in the Synthesis domain at Cadence Design Systems, Noida. He received his B.Tech. degree in Electronics and Communication Engineering from Jaypee Institute of Information Technology, Noida, India in 2016. His interest areas include frontend optimizations and mapping algorithms. His research interest is mainly in VLSI and EDA domain.

She received her B.Tech. degree in Electronics and Communication Engineering from Jaypee Institute of Information Technology, Noida, India in 2016. She is currently working as a Software Engineer in the Formal and IP verification domain at Cadence Design Systems, Noida. She received her B.Tech. degree in Electronics and Communication Engineering from Jaypee Institute of Information Technology, Noida, India in 2016. Her research interest is mainly in IP development and verification. Her research interest is mainly in VLSI, IP and EDA domain.

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